As the semiconductor packaging technology advances, there have been developed various types of packages for semiconductor components. For example, one type of semiconductor component allows a semiconductor chip having an integrated circuit (IC) to be embedded in and electrically integrated with a package substrate. This semiconductor component may desirably reduce the overall size and improve the electrical functionality thereof, and thereby becomes widely adopted.
Referring to FIGS. 1A to 1L, a method for fabricating a conventional package substrate embedded with a semiconductor chip disclosed in U.S. Pat. No. 6,586,276 is shown. As shown in FIG. 1A, a wafer 10 having a plurality of electrode pads 101 is provided. As shown in FIG. 1B, a passivation layer is formed on the wafer 10. As in FIG. 1C, a first opening 110 is formed in the passivation layer 11 to expose the electrode pads 101. As shown in FIG. 1D, the passivation layer 11 and the exposed electrode pads 101 are covered with an adhesion layer 12. As shown in FIG. 1E, a protection layer 13 is then formed on the adhesion layer 12. As shown in FIG. 1F, the wafer 10 is cut to form a plurality of semiconductor chips 10a. As shown in FIG. 1G, a substrate 14 having an opening 140 is provided, and then one semiconductor chip 10a is placed into the opening 140 of the substrate 14 and secured there by a bonding material 15 formed in the gaps between the opening 140 of the substrate 14 and the semiconductor chip 10a. As shown in FIG. 1H, a conductive layer 16 is formed on top of the protection layer 13 of the semiconductor chip 10a, the bonding material 15 and the substrate 14. As shown in FIG. 1I, a resist layer 17 is then formed on the conductive layer 16 having resist openings 170 at locations corresponding to those of the electrode pads 101. As shown in FIG. 1J, expanded pads 18 are electroplated onto portions of the conductive layer 16 within the resist openings 170. As shown in FIG. 1K, the resist layer 17 and the underlying conductive layer 16, protection layer 13 and adhesion layer 12 are removed to expose the expanded pads and the passivation layer 11, wherein the expanded pads 18 are larger than the electrode pads 101 to facilitate alignment during subsequent lamination of a dielectric layer(s) and a circuit layer(s). As shown in FIG. 1L, finally, a circuit build-up structure 19 is then formed on the electrode pads 18, the passivation layer 11 and the substrate 14. The circuit build-up structure 19 includes at least a dielectric layer 191, a circuit layer 192 laminated on the dielectric layer and conductive vias 193 in the dielectric layer electrically connected with the expanded pads 18. The circuit build-up structure 19 further includes a plurality of conductive pads 194 on the surface thereof for electrically connecting the circuit layer 192. An insulating protective layer 195 is also formed on the circuit build-up structure 19 having a plurality of openings 1950 that correspondingly expose the conductive pads 194.
As can be seen from the above, regarding a conventional package substrate embedded with a semiconductor chip, before dicing the wafer 10 into a plurality of semiconductor chips 10a, an adhesion layer 12 has to be formed on the passivation layer 11 and the electrode pads 101, and then a protection layer 13 is formed on the adhesion layer 12. Although the adhesion layer 12 and the protection layer 13 facilitate subsequent processes of the semiconductor chip in the substrate, the exposed portions of the adhesion layer 12 and the protection layer 13 have to be removed before lamination of the dielectric layer 191 and the circuit layer 192 can be performed. As a result, the formation of the expanded pads 18 and electrically connection cannot be performed at the same time, which increases manufacturing cost and time. Furthermore, the electrically connecting structure including the expanded pads 18 and the conductive vias 192 is a complicated structure.
Therefore, there is a need for a package substrate embedded with a semiconductor component, which enables reduction of manufacturing costs and time as well as structural complexity.